When a digital computer system is initialized upon power-up or reset, the entire system memory is usually tested for both address line and data faults. This is typically accomplished by writing a unique data pattern to every memory location starting at the lowest address and ending at the highest address. The contents of each location are then read and compared to the expected data to determine if the stored data pattern is correct. The inverse of the pattern may then be written to each memory location in the same ascending or even descending sequential order. Again, the data pattern is read and compared to ensure correct addressing and data integrity.
Although the type of method described above will detect both address line failures and a large portion of data failures within the array, the time required by such a test method to test a large memory array makes this approach unacceptable to the system user.
Therefore, a need exists to provide an improved method of achieving reduced initialization time without compromising the level of critical fault test coverage or limiting system performance while testing large memory arrays.